1. Field of the Invention
The present invention relates to a method for the self-alignment of metal contacts on semiconductors, wherein a sidewall is used to reserve a submicronic distance between two neighboring regions controlled by two metallizations. The invention can be applied to semiconductor devices such as transistors and, more specifically, to those working in microwave applications where the safety distances between neighboring regions are sometimes submicronic.
2. Description of the Prior Art
It is known that, in a transistor such as the one shown schematically in FIG. 1, comprising at least one substrate 1, one active layer 2, one control region 3 with its metallization and two access electrodes 4 and 5, it is important to reduce the distances referenced "d" between two neighboring regions. In the particular example shown, if the transistor is a field-effect transistor, it is important, for several reasons, to reduce the distance "d" between the source 4 and the gate 3 and the distance "d" between the gate 3 and the drain 5.
The distance "d" considered in the active layer 2, determines the values of resistance to access from the source region 4 and drain region 5 to the region controlled by the gate 3 in the active layer 2, and these access resistance values come into play in the characteristics of the transistors. The access resistance values will therefore be minimal, and the characteristics of the transistors will be improved if the distances "d" are reduced without, however, being cancelled for it is these distances that govern the voltage strength of a transistor. An optimum value would be of the order of 100 nm, namely 0.1 micrometer.
The method used should, however, retain the possibility making additional coatings, to the metallizations of the electrodes, of AuGe/Ni/Au alloy which reduces the resistivity of the contacts.
However, it is also known that the presently used techniques are not entirely satisfactory, and that the development of microwave transistors or integrated circuits with very large-scale integration comes up against these problems of submicronic geometries.
The usual technique of UV photolithography, owing to its relative lack of precision in the alignment of the masks, leads to high, non-reproducible values of access resistance, and the distances "d" are rarely smaller than one micron (1000 nm).
In certain T gate or capped gate techniques, the access resistance is determined by a chemical sub-etching of the material of the gate region 3, beneath the metallization, but poor control of the sub-etching leads to non-reproducible access resistance values.
Finally, the sidewall technique has been adopted to self-align an ion implantation process. However, this technique entails a delicate step as shown in FIG. 2.
Briefly, the sidewall method consists in covering a pattern 6, in the form of a mesa on the surface of the semiconductor wafer 1+2, with a uniform layer of an insulator such as silica. By reactive ionic etching (RIE), this layer is eliminated except at 7, on the flanks of the pattern 6: the thickness of the layer 7 defines the distance "d" separating two neighboring regions in the active layer 2, with high precision, namely the precision obtained by the growth of a layer that can be efficiently controlled.
However, during the self-aligned deposition of the metallizations of the electrodes 3, 4 and 5, it often happens that a fine metal film 8 gets deposited on the flanks of the sidewall 7, entailing the risk of a short-circuit between electrodes. The removal of this residual metallization 8 by an inclined ionic machining of the flank of the "sidewall" is a delicate task, for there is a risk of its causing deterioration in the insulating properties of the sidewall 7, by surface conduction after irradiation.